As display technique develops rapidly, a display emerges a trend towards development of high integration and low cost. Herein, Gate Driver on Array (GOA) technique integrates a thin film transistor (TFT) gate switching circuit on an array substrate of a display panel to form scanning drive of the display panel, so that wiring space of bonding region and fan-out region of a gate integrated circuit (IC) could be saved. It could not only reduce products' cost on material and manufacturing process, but also enable the display panel to realize an artistic design with symmetrical on both sides and narrow frame. Furthermore, such integration process could also spare bonding process in a direction of gate scanning line, so as to raise productivity and yield rate.
The GOA circuit is generally composed of multiple shift registers connected in cascades. A driving signal output terminal of each stage of shift register is corresponding to one gate line respectively, and is used to arrange respective gate lines along a scanning direction sequentially. For the existing GOA circuit, scanning time length for each row of gate lines is generally fixed. Therefore, the existing GOA circuit is not suitable for use in some display devices that need to adjust the scanning time length of each row of gate lines according to actual situation.
At present, although adjusting of the scanning time length could be realized by using different clock control signals, it needs to use a plurality of clock controllers. Furthermore, for different scanning time lengths, cascading relationships of shift registers in the GOA circuit are also different, thereby resulting in that application of the existing GOA circuit into the display devices that need to adjust the scanning time length of gate lines according to actual situation becomes more difficult and manufacturing cost increases, such that these display devices are not competitive.